Overview of Role
As a Physical Design Verification Engineer, you will be responsible for the Design Rule Check, Layout vs. Schematic checking and fix all PDV/EMIR/Noise/SigEM violations and errors. You may also do customization and implementation of top clocks and implement timing ECOs on high performance blocks. You will be reporting to Senior Manager of Advanced Chip implementation team at its San Jose Design Center, San Jose, CA and joining a team of engineers dedicated to pushing the envelope for the world’s leading semiconductor company. We are currently operating in a hybrid work schedule with 3 days in office.
Responsibilities
- Perform the following:
- DRC/LVS/ERC/ANTENNA analysis and clean up
- Floorplan analysis and congestion solution
- Power IR/EM analysis and fix
- Signal EM/Noise analysis and fix
- Physical verification sign off
- Implement ECOs for timing closure
- Customized Clock tree structure
- May also perform floorplan, place and route
Minimum Qualifications
- Master’s degree in Electrical/Computer Science Engineering with 3+ years of industry experience, or Bachelor’s degree in Electrical/Computer Science Engineering plus 5+ years of industry experience
- In depth knowledge of major EDA tools/design flows
- Experience with TSMC N16 or below technology
- Experience in block level implementation or chip integration and signoff
- Experience in Perl/TCL language programming
- Proven record in multi-million gate design production tapeouts
- Ability to work regularly at a Customer site in the South Bay area
Preferred Qualifications
Experience in any of the following:
- TSMC N16 and below technology
- Chip level integration, and wire editing
- Low-power implementation methodology
- Able to independently complete Netlist-GDS P&R, signoff task
Company Description
As a trusted technology and capacity provider, TSMC is driven by the desire to be:
- The world’s leading dedicated semiconductor foundry
- The technology leader with a strong reputation for manufacturing excellence
- Advancing semiconductor manufacturing innovations to enable the future of technology
TSMC pioneered the pure-play foundry business model when it was founded in 1987 and has been the world’s leading dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry’s leading process technologies and a portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world. In North America, TSMC has a strong sales and service organization that works with customers by helping them achieve silicon success with cutting-edge technologies and manufacturing excellence. The Company has continued to accelerate its R&D investment and staffing in recent years and is expanding its manufacturing footprint to support customer innovation with 3D IC technologies and optimal manufacturing capacity.
Diversity statement
TSMC Technology, Inc. is committed to employing a diverse workforce and provides Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, or any other characteristic protected by applicable law.
Pay Transparency Statement
At TSMC, your base pay is only part of your overall total compensation package. At the time of this posting, this role typically pays a base salary between $161,500 and $198,000. The range displayed reflects the minimum and maximum target for new hires. Actual pay may be more or less than the posted range. Factors that influence pay include the individual's skills, qualifications, education, experience and the position level and location.
TSMC’s total compensation package consists of market competitive pay, allowances, bonuses and comprehensive benefits. We also offer extensive development opportunities and programs.